Sunday, 13 December 2015

Zynq design steps

  1. Design component in MATLAB
  2. Test component in MATLAB
  3. Generate IP core
  4. Verify & Optimize IP core
  5. Create base project in Xilinx Vivado
  6. Connect IP core to processing system in base project
  7. Generate bitstream
  8. Program FPGA
  9. Create software to interface with FPGA
  10. Test system with component
  11. Repeat for each component

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